Intel's new roadmap: faster, sooner

Just a week after announcing the first delay in its 64-bit IA-64 CPU,code-named "Merced", Intel has modified plans for their 32-bit line ofmicroprocessors and speed freaks are going to be pleased: Delivery datesfor upcoming chipsets--including the

Paul Thurrott

June 4, 1998

2 Min Read
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Just a week after announcing the first delay in its 64-bit IA-64 CPU,code-named "Merced", Intel has modified plans for their 32-bit line ofmicroprocessors and speed freaks are going to be pleased: Delivery datesfor upcoming chipsets--including the Katmai and Tanner--have all been bumped up, and higher-speed versions of all of Intel's chips are going tocome sooner than previous announced.

The biggest change comes to the chip code-named "Tanner", which was originally conceived as a stepping-stone to Merced. Tanner was expected tobe the ultimate Pentium II chip, and was going to fit into the so-calledSlot-M that the Merced will use, offering users a way to upgrade easily tothe 64-bit Merced when it is released. Now, Tanner will be released as aPentium II Xeon processor instead, meaning it will work with the Slot 2slot used by other Xeons and will not be positioned as a transition chipfor Merced. The biggest benefit of this new approach is time: Instead ofdebuting in mid-1999 as planned, Tanner CPUs will appear in early 1999. Thefirst "Tanner" Pentium II Xeon will run at 500 MHz and feature the MMX-2 instruction set.

MMX-2, code-named "Katmai", goes far beyond the MMX instruction set nowfound in all Pentium II and Pentium MMX microprocessors. Katmai offers acomplete 3D chipset right in the CPU, speeding graphics and gamingapplication. MMX-2 will also be finding its way into the Pentium II line,with 450 MHz and 500 MHz Pentium IIs featuring the instructions now expected in early 1999.

Also moving forward is the next-generation of the Celeron line, which isgeared toward what Intel calls "basic PCs". The Celeron will be upgraded to300 MHz and 333 MHz late this year, while they will gain 128K L2 cache (thecurrent models have no L2 cache; Pentium II CPUs have 512K).

While the cynical may ponder whether these moves were designed to offsetthe bad press generated when Intel delayed Merced, the company says thatincreased manufacturing efficiencies generated improvements in their volumeyields that made this possible. Also, the company is swiftly moving to a new .25 micron process, which makes their chips smaller, faster, and runcooler than was previously possible

About the Author

Paul Thurrott

Paul Thurrott is senior technical analyst for Windows IT Pro. He writes the SuperSite for Windows, a weekly editorial for Windows IT Pro UPDATE, and a daily Windows news and information newsletter called WinInfo Daily UPDATE.

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