Profusion Raises SMP to New Levels
Quickly brush up on Profusion architecture's development.
February 9, 2000
Although the four-way SMP server architecture that is based on Intel's 450NX chipset, which Figure A shows, provides good scalability with as many as four CPUs, the architecture's limitations make it unsuitable for 8-way SMP systems. The 100MHz processor bus, for example, supports a maximum of only five loads (four processors and the chipset), limiting the number of additional processors. The overall processor bus and memory bandwidth also need to increase to ensure scalability with additional CPUs. Finally, the architecture's 2-bit coding technique for identifying CPUs can support only four processors per bus.
To address these limitations, Intel settled on Profusion, a new architecture that the company acquired when it purchased Corollary in 1997. This new architecture provides two 100MHz processor buses for CPUs, a third 100MHz 64-bit bus dedicated to I/O traffic, and two independent paths to interleaved Synchronous DRAM (SDRAM). These buses and paths connect to the Profusion chipset's nonblocking five-point crossbar switch and provide simultaneous read and write paths, as Figure B illustrates.
One potential problem with 8-way servers is that Intel's snooping algorithm, which maintains cache coherency, could require substantial processor bus bandwidth and CPU cycles. The Profusion architecture minimizes this unwanted bus traffic and CPU utilization by using cache coherency filters (which Compaq calls system cache accelerators) on each CPU bus. The filters maintain the addresses and state information of data in the Level 2 caches on each corresponding bus. When a memory transaction occurs, the local processor bus checks the remote coherency filter and snoops the remote CPU bus only when the processor bus detects a cache coherency problem.
The Profusion architecture provides two ports to main memory and supports up to 32GB of SDRAM to improve memory bandwidth. The two memory banks are cache-line interleaved and share a common address range. One port responds to even-numbered cache lines, and the other port responds to odd-numbered lines.
The Profusion architecture also enhances server I/O. The chipset dedicates a third 100MHz 64-bit bus to I/O traffic. With Profusion, Intel introduced a new 64-bit PCI bus bridge chip, the PB64, that the company codeveloped with Compaq. This new chip supports as many as two 66MHz 64-bit PCI slots or four 33MHz 64-bit slots per bridge. The I/O bus supports as many as four PB64s in one server. Because the bridge chip features an integrated hot-plug controller, you can swap PCI adapters without powering down the server. Intel's introduction of the Profusion architecture extends the limits of performance and scalability and brings 8-way servers into enterprise computing's mainstream. To learn more about Profusion, see Tao Zhou, "Profusion Architecture," November 1999.
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