Are Open Source RISC-V CPUs Destined for the Server Market?

One thing that was evident at the December 2019 RISC-V Summit in San Jose, Calif., is that the RISC-V open source instruction set architecture, meant for designing and manufacturing silicon chips, is a rising star in the hardware world. The big question right now is whether the project will forever remain in the CPU-helper space it currently occupies, or will we be seeing RISC-V CPUs being deployed in data center servers.

There are many reasons why device makers are eager to embrace RISC-V silicon, starting with price. Naveed Sherwani, CEO of SiFive, a company that earns its keep by walking device makers through the process of designing and manufacturing RISC-V chips, has said that by using the ISA, a chip can be brought to market for approximately 10% of the costs normally incurred in using other chip architectures.

Security is also built in, unlike offerings from Intel, AMD and Arm, which are based on designs from the 1980s, a time when security was an afterthought.

Add to that RISC-V's modular design – a chip can be customized to exactly match a device's requirements, freeing designers from having to make design trade-offs to accommodate an off-the-shelf chip – and it's easy to understand why more than 100 organizations have paid to sign on as members of the RISC-V Foundation, which maintains the ISA.

Although silicon made from the RISC-V design have so far been "helper" chips, used primarily as accelerators and microcontrollers to take the load off of main processors, all indications are that full-fledged RISC-V CPUs are on the horizon, especially for use in embedded Internet of Things systems and in small energy-sipping servers located in small edge data centers that are now beginning to be built at the base of cell towers.

Red Hat, a RISC-V Foundation member since August, certainly seems to think that's coming. In a presentation, the software company demonstrated the work it's been doing to incorporate the silicon into its hybrid cloud offerings by running containers on RISC-V CPUs using SiFive's HiFive Unleashed developer board as well as x86-based RISC-V emulators.

Carlos Eduardo de Paula, Red Hat's senior cloud architect, led the session and said that although work is still ongoing, Red Hat already has the orchestration engine Kubernetes running flawlessly, as well as k3s, the minified version of Kubernetes for embedded systems; Prometheus, the Cloud Native Computing Foundation's event monitoring software; and other container-related applications.

Although nothing was said during the session about the expected use cases for these efforts, afterwards de Paula confirmed for ITPro Today that "it's targeting data center workloads in the future where you have clusters on IoT or edge computing."

The arrival of RISC-V servers might be sooner than most people are anticipating.

For the last couple of years, since about the time that Western Digital became a major investor in SiFive and vowed to use RISC-V silicon exclusively in it's products, the pace of RISC-V development has been rapidly accelerating. In June, SiFive's Sherwani told me that if a year earlier he "thought that cellphones are five years away and servers are 10 years away," he would now say that "cellphones and laptops are two years away, and servers are five years away. That is how much it has changed in the last year."

However, even though it seems pretty much certain that RISC-V CPUs will eventually be available for use in everything from phones to servers, that near-term possibility seemed to be off-the-table and was barely broached at the summit. Most discussions, especially in the keynotes, centered around RISC-V cores being used as CPU-helpers, the area where the architecture is already finding success.

RISC-V CPUs and servers almost seemed to be taboo. So much so that Martin Fink, who's been Western Digital's adviser to the CEO since stepping aside as CTO in August, went so far as to pooh-pooh the notion of server-class RISC-V CPUs in a conversation with ITPro Today.

“[S]ome people think data center means building a Zeon class processor, but instead of having x86 cores it has RISC-V cores,” he said. “I have no interest in building that; I don’t see the point in doing that. Intel’s pretty much done a really good job. Let’s let them keep doing what they’re doing right.”

Western Digital's core data center storage business requires plenty of specialized silicon apart from main CPUs – and to that end it has developed SweRV, a RISC-V core it says will be used to the tune of 200-400 million annually in its own products.

But it might be just as true that the folks behind RISC-V are choosing their battles wisely, and striving to stay beneath Intel’s radar until the time is right to release a CPU anchored by the ISA.

A year ago, at the first RISC-V Summit, SiFive's cofounder and CTO, Yunsup Lee, just about said as much in a conversation with ITPro Today when he downplayed the importance of a desktop or server-ready RISC-V CPU and added, "Why would you go fight that battle with Intel right now?"

Even if the RISC-V folks aren't yet prepared to take on Intel or AMD, they do seem ready to go head-to-head with Arm, where they're competitive on price and outperform in the energy consumption arena that has traditionally been Arm's playing ground.